Responsibilities will include but not limited to following:
- Hands-on Design experience in High-Speed PHY/IO, IO receiver/transmitter, Bias Blocks (Voltage Current references), in N3/N2 nodes.
- Verification of Block Modules end-to-end: AC, DC, Transient, Noise, PERC, EM IR, Reliability checks, Co-Simulations of Analog + Digital (RTL) etc.
MS Visio is good to have.
- Independently guide Layout Engineer perform Post-Layout Design fix iterations.
- Debug functional and performance issues in simulations
- Flexible to take different tasks in project.
- Execute tasks with minimum supervision/tracking.
- Have accountability and ownership on blocks tasks assigned.
- Design implementation to meet PPA goals.
- Create and check all relevant design views using sign-off tools.
Required Skills:
- B.Tech/B.E./MS /M.E. /M tech/Ph.D. in Electrical Engineering
- 6+yrs experience with Cadence schematic capture, Virtuoso, Spectre, HSPICE circuit simulation tools.
- Proficiency in AMS/High speed custom digital design flows, tools, and methodologies.
- Basic exposure to layout techniques with attention to review the layouts and provide constraints.
- Knowledge of scripting (SHELL, PERL, SKILL), Excel macros MS Visio is positive to have.
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