Functional Verification Engineer for DDR Memory Controller and Phy IP development team.
The role would include functional verification of the DDR Memory Controller and Phy IP solution.
BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer, with a large portion of the recent work experience on verification environment development.
Robust background on functional verification fundamentals, environment planning, test plan generation, environment development are a must.
System Verilog experience and experience with UVM based functional verification workplace development is required.
Prior RTL Design experience using Verilog is a must - so that the verification engineer is self-sufficient for most aspects of debugging.
Latest DDR Protocol experience is highly desirable. Prior experience in functional verification and debugging of complex protocols is
Skills:
UVM, OVM, SV, DDR, PCIe, PHY, Ethernet
Job Location:
Bangalore | Hyderabad | Noida
Experience:
5+ years
Company Name:
EDA Semiconductor RD
Disclaimer : This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.