We are seeking an experienced RTL Design Engineer with robust expertise in digital IC design, micro-architecture development, and RTL implementation for ASIC/FPGA-based products. The candidate will be responsible for developing high-quality RTL designs, supporting integration activities, and working closely with verification and physical design teams.
Key Responsibilities
Analyze specifications and develop micro-architecture for digital IPs and subsystems.
Design and implement RTL using Verilog/ System Verilog.
Perform RTL quality checks including linting, CDC/RDC analysis, and synthesis readiness.
Support SoC/IP integration activities.
Participate in design reviews and technical discussions.
Collaborate with verification teams to resolve design issues and achieve quality sign-off.
Support FPGA prototyping and silicon bring-up activities as required.
Prepare and maintain design documentation.
Required Skills
Robust proficiency in Verilog/SystemVerilog RTL coding.
Good understanding of digital design fundamentals, FSMs, pipelining, clock-domain crossing, and timing concepts.
Experience in ASIC/FPGA design and development flows.
Knowledge of synthesis, timing analysis, lint, and CDC tools.
Strong debugging and problem-solving skills.
Protocol Experience (One or More)
PCIe
Ethernet (1G/10G/25G/100G)
AXI/AHB/APB
DDR/LPDDR
NVMe
USB
I2C/SPI/UART
MIPI
Preferred Qualifications
Exposure to SoC architecture and integration.
Experience with FPGA platforms and prototyping.
Knowledge of Functional Safety standards such as ISO 26262 is a solid advantage.
Experience with safety mechanisms and safety-related design development is a plus.
Education
B.E./B.Tech/M.E./M.Tech in Electronics, VLSI, Electrical Engineering, or related disciplines.