Location: Hyderabad
Experience: 5+ Years
Notice Period: Immediate to 30 Days Preferred
Required Skills:
• 5+ years of experience in Emulation, RTL Design, or Verification.
• Solid knowledge of Verilog/SystemVerilog.
• Hands-on experience with emulation platforms such as Cadence Palladium, Siemens Veloce, and Synopsys ZeBu.
• Valuable understanding of SoC Architecture and Verification Methodologies.
• Experience with Debug Tools, Waveform Analysis, and Performance Tuning.
• Familiarity with interfaces/protocols such as PCIe, DDR, Ethernet, and AMBA (AXI/AHB/APB).
• Experience with scripting languages such as Python, Perl, or Shell.
• Bachelor's/Master's degree in Electronics, Electrical Engineering, or a related field.