We are seeking an experienced RTL Design & Verification Engineer with solid expertise in digital IC design, micro-architecture development, RTL implementation, and functional verification for ASIC/FPGA-based products. The candidate will be responsible for developing high-quality RTL designs, creating and executing comprehensive verification plans, building verification environments, and working closely with design, verification, and physical design teams to ensure successful product delivery.

Key Responsibilities
Develop micro-architecture and implement RTL using Verilog/SystemVerilog.
Design and integrate IPs, subsystems, and SoC components for ASIC/FPGA projects.
Create and maintain verification settings using SystemVerilog and UVM.
Develop test plans, test cases, assertions, and coverage models.
Perform functional verification, debug design issues, and analyze simulation results.




Collaborate with design, verification, synthesis, and physical design teams.
Support RTL integration, synthesis, and timing closure activities.
Ensure verification completeness and quality through coverage-driven methodologies.

Required Skills
Strong experience in RTL Design and Verification.
Proficiency in Verilog/SystemVerilog.
Expertise in UVM-based verification methodologies.
Valuable understanding of digital design fundamentals and micro-architecture.
Experience with ASIC/FPGA design and verification flows.
Knowledge of simulation, debugging, and coverage analysis.
Familiarity with synthesis, timing analysis, and STA concepts.
Strong problem-solving and communication skills.

📌 Rtl Design/verification Engineer Hyderabad
🏢 Tata Elxsi
📍 Hyderabad