Role Description
Additional Comments:Physical Design Engineer Experience- 4 to 10 years
Engineers is expected to be very valuable in Basic Fundamentals of C-MOS technology
Expected to have a very positive understanding of the PD Flow for flat and hierarchal designs
Able to handle RTL/Netlist to GDSII independently at block level/SS/SoC and should have done multiple tape outs with low power implementation (Experience on floor planning, Partitioning, integration at Subsystem/Chip will be add advantage)
Should have hands-on experience of working on Lower technology nodes like 3nm, 5nm, 7nm, 10nm, 14nm, 16nm, 28nm etc.
Hands-on experience in floor planning, placement optimizations, CTS and routing. Hands-on experience in block/top level signoff STA,



physical verification (DRC/LVS/ERC/antenna) checks and other reliability checks(IR/EM/Xtalk)
Should have expertise on industry standard EDA tools from Synopsys , Cadence and Mentor
( ICC2, Fusion-Compiler, Design Compiler, Primetime, PTSI, IC Validator, Innovus, Genus, Tempus, Encounter, Nanoroute, Calibre, StarRC and Redhawk, voltage storm
Exposure in DMSA flow for ECO generation and implementation.
Positive knowledge of VLSI process and scripting in TCL, perl .

Skills

Physical design,PNR,PD Flow

📌 Associate Iii Vlsi Pnr Aster Bengaluru (India)
🏢 UST
📍 India