GLS Verification Engineer

Experience: 3 to 6 Years

Location: Bangalore

Role Objective The candidate will be responsible for the verification of complex SoC/IP netlists. You will ensure functional correctness and timing closure post-synthesis and post-layout, bridging the gap between RTL and Silicon.

Key Responsibilities
GLS Strategy & Execution: Define and execute the Gate Level Simulation plan for block and SoC levels, including zero-delay and SDF back-annotated simulations.
Workplace Setup: Port existing SV/UVM testbenches from RTL to GLS settings.
Debug Mastery: Root-cause complex "X-propagation" issues, timing violations (Setup/Hold), and uninitialized memory/flop states in the netlist.
Formal Verification: Perform Logic Equivalence Checking (LEC) using Cadence Conformal to ensure RTL-to-Netlist and Netlist-to-Netlist (Post-ECO) consistency.
Low Power Verification: Run Power-Aware GLS (PA-GLS) to verify UPF/CPF implementation, level shifters, and isolation cells.
DFT Integration: Validate Scan chains,



MBIST, and ATPG patterns at the gate level to ensure DFT logic doesn't break functional paths.

Technical Skills Required
Core DV: 3+ years of experience in SystemVerilog and UVM .
Simulator Expertise: Hands-on experience with Cadence Xcelium (formerly Incisive/NC-Sim).
Timing Knowledge: Deep understanding of Static Timing Analysis (STA), SDF file structures, and how to handle timing-checks/force-releases.
Scripting: Proficiency in Python , Perl, or Shell scripting to automate simulation regressions and log parsing.
Protocols: Knowledge of standard protocols like AXI, AHB, PCIe, or DDR is highly preferred.

Preferred Qualifications
Experience with Cadence Palladium or Zebu emulation for accelerating GLS is a significant plus.
Familiarity with 5nm/7nm process nodes and associated physical design challenges.

📌 Gls Verification Bengaluru (India)
🏢 ACL Digital
📍 India