Positive understanding of ASIC design flow.
Hands on experience in synthesis and static timing analysis.
Proficiency with Synopsys DC & PT tools and Verilog/VHDL is a must.
Experience in Perl, TCL and shell scripting is desirable.
Excellent interpersonal & analytical skills with ability to work independently.
Placement/Power aware synthesis using Synopsys & Cadence tools (DCG/NXT/FC, Genus).
Constraints development, Formal Verification, CECO, Static Timing Analysis & timing closure.
Work closely with design team to come up with preplacement requirements & timing constraints.
Work closely with physical design team for floorplan, placement & timing reviews.
Work closely with cross-functional teams to review standard cell profile, timing models & memory models.
Expertise in physical verification (LVS, ERC/PERC, DFM, OPC,



Tape Out process) of SoC/Full-chip-level and/or block-level.
Preferably worked on 5nm/7nm/12nm/14nm/16nm/22nm nodes at the major foundries.
Experience in developing sign-off methodology/flow to and supporting a larger team

Experience (years) : 7+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

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📌 Synthesis Lead Bengaluru
🏢 Mirafra
📍 Bengaluru