Job Title: IP Design Verification (IP DV) Engineer Location: Bangalore

Experience: 5 15 Years

We are looking for an experienced IP Design Verification Engineer with robust expertise in verifying high-speed IPs and developing robust verification environments. The ideal candidate should have hands-on experience with Ethernet, DDR, USB, PCIe , and Power-Aware Verification (UPF) using SystemVerilog/UVM methodologies.

Key Responsibilities
Develop and execute verification plans for complex IPs.
Build and maintain SystemVerilog/UVM based verification environments.
Verify and debug Ethernet, DDR, USB, and PCIe IPs.
Perform functional verification, regression testing, coverage closure, and debug.
Implement and validate Power-Aware Verification using UPF.
Work closely with Design, Architecture, and Validation teams to resolve functional issues.
Analyze failures,



root cause issues, and ensure high-quality verification closure.

Required Skills
Strong experience in SystemVerilog (SV) and UVM.
Hands-on experience with Ethernet, DDR, USB, PCIe IP Verification.
Positive understanding of UPF/Low Power Verification.
Experience with functional coverage, assertions (SVA), regression, and debugging.
Knowledge of industry-standard simulation and debug tools.
Robust debugging, analytical, and communication skills.

Preferred Skills
Experience in ARM/SoC environments.
Knowledge of scripting languages such as Python, Perl, or Shell.
Exposure to ASIC/SoC verification flow and verification methodologies.

📌 Ip Verification Bangalore Urban
🏢 Cortex Consultants
📍 Bangalore Urban