Job Description: • Responsibilities include packing RTL files into IP using AMD packaging methodology
• Resolving packing level challenges, GUI wizard development and verifying the IP generated through Vivado tool.
• Candidate must have excellent TCL and PERL/Python concepts and experience in Verilog / SystemVerilog design and verification.
• Working knowledge of UNIX workplace desired.
• Knowledge of AXI4/APB bus protocols.
• Positive waveform debug skills using front end industry standard design tools like VCS, xcelium and Questa.
• Expertise with FPGA architecture and Xilinx-AMD implementation tools (Vivado) valuable to have.
• Excellent communication and problem-solving skills.
Qualification: B.E/M.E/M.Tech or B.S/M.S in EE/CE
📌 Fpga Opening 4 To 8yrs Hyd Mirafra Technologies Hyderabad
🏢 Mirafra
📍 Hyderabad
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