SmartSoC, a Virtusa Company , is a leading semiconductor engineering services organization specializing in end-to-end ASIC, SoC, FPGA, Embedded Systems, and VLSI design solutions. Backed by Virtusa's global engineering capabilities, SmartSoC partners with leading semiconductor companies to deliver cutting-edge, high-quality silicon solutions across the entire chip development lifecycle.

Looking For : STA Lead

Work Location: Bangalore

Experience: 6+ Years

Availability: Immediate or currently serving notice candidates is preffered

Key Responsibilities
Timing Closure Leadership: Deliver sign-off quality STA across complex, high-frequency designs, ensuring robust performance in diverse modes and corners.
Customer Impact: Translate technical excellence into measurable outcomes for customers — faster turnaround, improved QoR, and optimized PPA trade-offs.
Constraint Development: Architect and validate timing constraints to guarantee design reliability and seamless integration into customer workflows.
Synthesis & Optimization: Own synthesis flows using Fusion Compiler and Design Compiler, achieving customer-defined targets for timing, area, and power.
Cross-functional Collaboration: Partner with RTL,



PD, and DFT teams to proactively resolve design challenges, ensuring smooth delivery for customer programs.
AI-driven Design: Apply reinforcement learning tools (DSO.ai) to accelerate design space exploration, delivering cutting-edge solutions that reduce cycle time.
Low Power & UPF: Implement and verify UPF-based power intent, ensuring energy-efficient designs aligned with customer requirements.
Formal Equivalence & ECOs: Guarantee functional correctness through formal verification and ECO generation, enabling reliable customer tape-outs.

Qualifications:
Bachelor’s degree in Electrical Engineering from reputed universities
7+ years of semiconductor design experience at leading companies
Expertise in STA, synthesis, constraints, and low-power verification.
Proficiency in industry-standard tools: PrimeTime, Fusion Compiler, Design Compiler, Formality, ICC2, Conformal, VCLP.
Solid programming skills in TCL, Python, Perl, and Verilog.
Deep understanding of advanced node challenges (cross talk, OCV, AOCV, POCV) and clock architectures.

📌 Senior Physical Design Engineer Bangalore Metropolitan Area
🏢 SmartSoC Solutions
📍 Bangalore Metropolitan Area