About the Role We are looking for a skilled Design Verification Engineer to join our team and work on next-generation semiconductor designs. You will be responsible for verifying complex System-on-Chip (SoC) architectures to ensure high-quality, reliable silicon.

Key Responsibilities - 3 - 7 years of experience in Design Verification
Develop and execute verification plans for SoC/IP level designs
Build and maintain testbenches using System Verilog/UVM
Write test cases, sequences, and assertions to validate functionality
Perform functional, regression, and coverage-driven verification
Debug failures and work closely with design teams to resolve issues
Analyze coverage metrics and improve test quality




Participate in reviews of design and verification settings Required Skills - Robust experience in System Verilog and UVM (Universal Verification Methodology)
Positive understanding of SoC architecture and digital design concepts
Experience with simulation tools (e.g., Synopsys VCS, Cadence Xcelium)
Knowledge of debugging using waveforms and logs
Familiarity with protocols like AMBA (AXI, AHB, APB)
Scripting knowledge (Python/Perl/Shell) is a plus Preferred Qualifications - Experience with low-power verification
Exposure to formal verification tools
Understanding of embedded systems or firmware interaction

📌 Senior/ Lead Design Verification Engineer Bengaluru (India)
🏢 Prodapt
📍 India