We are seeking a highly skilled

Principal Engineer for our Static Timing Analysis (STA)

function to ensure the timing performance and integrity of our complex semiconductor designs.

Key Responsibilities
Own complete STA signoff for ASIC and provide guidance to the PnR team.
Work with IP and Design teams for Timing constraints development and review.
Develop and implement advanced STA methodologies to meet timing closure requirements.
Collaborate with cross-functional teams including design, verification, and physical design.
Maintain STA scripts and tools to automate and streamline processes.

Requirements
Bachelor’s or Master’s degree in Electrical or Computer Engineering.
Minimum 8 years of experience in Static Timing Analysis.
In-depth knowledge of STA tools such as Synopsys PrimeTime and Cadence Tempus.
Solid understanding of digital design principles and physical design.
Experience with advanced process nodes (5nm, 3nm) is highly desirable.

📌 Staff Asic Digital Engineer Bengaluru (India)
🏢 Hunt Remotely
📍 India