Principal DFT Engineer

Experience: Not Available to Not Available years

Location: Pune, Maharashtra, India

Skills: DFT, Scan Architecture, JTAG, Memory BIST (MBIST), Logic BIST (LBIST), ATPG (Automatic Test Pattern Generation), Silicon Support, Static Timing Analysis (STA), Verilog, SystemVerilog, DFT-specific timing constraints (SDC files), Gate-level simulations (GLS), Automated Test Equipment (ATE), Synopsys TestMAX/DFT Compiler, Mentor Graphics Tessent, Cadence Modus, Tcl, Python, Perl

Job Description
We are looking for a Principal HW DFT Engineer who will architect, implement, and validate in-vehicle networking devices as part of NXP’s Automotive grade products. You will be responsible for advanced test strategies and implementation, verification and validation of pre/post tapeout of DFT features, overall test coverage improvements, and work closely with RTL and physical team on DFT timing constraints and closures.

Main Job Tasks and Responsibilities:
Architecture & Strategy: Define and implement advanced DFT strategies, including Scan Architecture, JTAG, Memory BIST (MBIST), and Logic BIST
Implementation & Verification: Lead the integration of digital subsystems, perform scan insertion, and generate ATPG (Automatic Test Pattern Generation) patterns while ensuring high fault coverage.
Silicon Support: Drive post-silicon validation and debug activities to root cause failures and improve manufacturing test efficiency.
Collaboration: Coordinate with physical design and test engineering teams to ensure timing closure and that test patterns are operational immediately upon silicon arrival.

Minimum Required Qualifications
Education:
B.S./M.S. Electrical/Computer Engineering (or similar degrees)
Experience:




Typically requires 10+ years of industry experience in SoC DFT implementation, verification, static timing closure, test coverage analysis and improvement, and silicon bring-up on ATE
Tool Expertise: Proficiency with industry-standard EDA tools from Mentor Graphics/Siemens (Tessent), Cadence, or Synopsys
Technical Skills:
• DFT - Scan insertion and architecture, ATPG: Proficiency in generating test vectors to detect manufacturing faults like stuck-at, transition, and advanced faults
• Built-In Self-Test (BIST): Integration of Memory BIST (MBIST) for embedded SRAM/ROM and Logic BIST (LBIST) for autonomous logic testing
• Boundary Scan & JTAG
• Test Compression: Implementing techniques to reduce test data volume and application time, which is critical for large System-on-Chip (SoC) designs.
• Hardware Design & Implementation - HDL Proficiency: Solid command of Verilog or SystemVerilog for modifying RTL to insert test logic and writing test wrappers.
• Timing & Constraints: Knowledge of Static Timing Analysis (STA) and creating DFT-specific timing constraints (SDC files) to ensure test logic does not degrade functional performance.
• Verification & Debug - Simulation: Conducting gate-level simulations (GLS) and verifying DFT logic for correctness before fabrication.
• Post-Silicon Debug: Analyzing silicon data from Automated Test Equipment (ATE) to diagnose failures and improve manufacturing yield.
• Software & Tool Proficiency - EDA Tool Suites: Mastery of industry-standard tools such as Synopsys TestMAX/DFT Compiler, Mentor Graphics Tessent, and Cadence Modus.
• Scripting & Automation: Expertise in Tcl, Python, or Perl to automate test insertion flows, run simulations, and parse coverage reports.
More information about NXP in India... #LI-7013

📌 Principal DFT Engineer (Pune)
🏢 NXP Semiconductors
📍 Pune