We are seeking experienced Emulation Engineers with expertise in Model Build and hardware emulation environments. The candidate should have hands-on experience in preparing RTL for emulation, model compilation, partitioning, debugging, and supporting pre-silicon validation activities.
Key Responsibilities
- Build and maintain emulation models for SoC/IP designs.
- Prepare RTL for hardware emulation.
- Perform design partitioning and compilation.
- Debug build and runtime issues.
- Support pre-silicon validation using emulation platforms.
- Collaborate with DV and Design teams.
- Optimize emulation performance.
Required Skills
- 5+ years of experience in Hardware Emulation.
- Strong experience in Model Build.
- Hands-on experience with emulation platforms such as:
- Cadence Palladium
- Siemens Veloce
- Synopsys ZeBu
- Positive understanding of RTL design (Verilog/SystemVerilog).
- Strong debugging skills.
- Experience with Linux environment and scripting.
Preferred Skills
- Knowledge of PCIe or other high-speed protocols.
- Experience with SoC integration.
- Python/Perl/TCL scripting.