Job Description

- Minimum 3 4 years of experience in ASIC/DFT simulation and silicon validation.
- Detailed knowledge of DFT concepts, pattern simulation, silicon debug, and yield enhancement.
- In-depth knowledge and hands-on experience in ATPG and coverage analysis.
- Strong knowledge of memory verification, repair, and failure root-cause analysis.
- Experience with any of the following tools is required:
- ATPG: TestKompress
- MBIST: Mentor ETVerify
- Simulation: VCS preferred, ModelSim

- Expertise in scripting languages such as Perl, Shell, etc. is an added advantage.
- Ability to work in an international team and dynamic workplace with good communication skills.
- Ability to learn and adapt to new tools and methodologies.
- Ability to multitask and work on several high-priority designs in parallel.

Disclaimer : This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 DFT Engineer (Chennai)
🏢 incise infotech
📍 Chennai