In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i e Floorplanning Power Grid Design Placement CTS Routing STA Power Integrity Analysis Physical Verification Chip finishing Should have experience on Physical Design Methodologies in 130nm 180nm Should have experience on programming in Tcl Tk Perl to automate design process and improve efficiency Must have hands-on experience on PnR Suite from Synopsys Cadence Innovus ICC2 Solid experience on Static Timing Analysis PrimeTime - SI EM IR-Drop analysis PT-PX Redhawk Physical Verification Calibre Understanding the practical application of methodologies and Physical Design Tools Flow Automation and Improvements Experience in complex SOC integration Low Power and High Speed Design and Advanced Physical Verification Techniques Department Semicon India Associate Skills Required Physical Verification Static Timing Analysis STA Physical Design GF 28nm Cadence EDA tools Years Of Exp 3 to 15 Years Desirable Skills Physical Verification Static Timing Analysis STA Physical Design Designation Associate