Job Title: RTL Design Engineer

Experience: 412 Years

Location: Bangalore / Noida / Hyderabad (Work From Office/Hybrid) Employment Type: Full Time

Job Summary :

We are looking for a highly motivated RTL Design Engineer with robust experience in ASIC/SoC design. The candidate will be responsible for developing synthesizable RTL, micro-architecture implementation, RTL integration, and working closely with verification, DFT, synthesis, and physical design teams throughout the ASIC development lifecycle.

Key Responsibilities :
Develop synthesizable RTL using Verilog/SystemVerilog.
Design digital blocks based on architecture specifications.
Create micro-architecture documents from functional requirements. Perform RTL coding following industry coding standards.
Integrate RTL modules into SoC.
Debug functional and RTL issues. Perform Clock Domain Crossing (CDC) analysis and resolution.
Perform Lint analysis and fix violations.
Support synthesis, timing closure, and power optimization.
Collaborate with Verification, DFT, Physical Design, and Architecture teams.



Optimize designs for Performance, Power, and Area (PPA).

Required Skills :
Strong RTL Design experience. Verilog/SystemVerilog.
Digital Design Fundamentals.
FSM Design.
Combinational & Sequential Logic.
RTL Integration. Lint Analysis.
Clock Domain Crossing (CDC).
Reset Domain Crossing (RDC).
Synthesis concepts. Static Timing Analysis (STA).
Timing Closure basics. Power Optimization. AMBA Protocols (AXI/AHB/APB).
Robust debugging and analytical skills.

Preferred Tools
Synopsys Design Compiler
SpyGlass Lint
SpyGlass CDC
Verdi
DVE
QuestaSim
SimVision
Cadence Genus
PrimeTime
TCL Shell Python

Qualifications

B.E./B.Tech/M.E./M.Tech in Electronics ECE EEE VLSI Microelectronics Related Engineering Discipline Positive to Have FPGA Design Low Power Design (UPF) DFT awareness PCIe, Ethernet, USB, DDR, MIPI experience ASIC Design Flow knowledge

📌 Rtl Design Engineer Noida (India)
🏢 Qiskitq Technology
📍 India