Responsibilities
Design and build complete FPGA-based SoC applications using our C++ flow - writing HLS cores, integrating them into full systems (interconnect, IPs, firmware), and running them on real hardware.
Use these apps to drive regression/validation testing (functional correctness, performance, QoR, timing).
Act as an internal 'customer zero,' feeding hands-on findings into feature prioritization and roadmap decisions alongside the compiler teams.

Requirements/Qualifications
Firmware/embedded C++ development (drivers, RTOS/bare-metal, DMA/interrupts); high-level synthesis as a user (Vitis HLS, Catapult, SmartHLS, or similar - pragmas, pipelining, QoR analysis);
FPGA/SoC system design (AXI, memory hierarchies, IP integration); solid general software engineering (C++); and a test/quality mindset for complex toolchains.




Communicate well, thrive with ambiguity, and are excited about the future of C++-based hardware/software co-design.
Xilinx/AMD Vitis flow experience, SDK and boot gen flows
Expertise to build Embedded FPGA application and validate on Silicon
Testing Linux and Standalone Device Drivers
Overall 8+ years of experience in same domain.

Travel Time

0% - 25%

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📌 Senior Engin Hyderabad
🏢 Microchip Technology
📍 Hyderabad