Job Description

Position Overview:

We are seeking a highly skilled and experienced Senior Engineer for our Static Timing Analysis (STA) function. The successful candidate will be part to a team of talented engineers responsible for ensuring the timing performance and integrity of our complex semiconductor designs. This role requires a valuable understanding of STA methodologies, prior experience of timing signoff and a strategic vision to drive continuous improvement in our timing analysis processes.

Key Responsibilities:
Own Subsystem level STA , providing direction and guidance to PnR team for Timing closure & Synthesis report analysis.
Develop and implement advanced STA methodologies and strategies to meet the timing closure requirements of complex IC designs.
Collaborate with cross-functional teams, including design, verification, physical design, and DFT,



to ensure seamless integration and optimal timing performance.
Drive the development and maintenance of STA scripts and tools to automate and streamline timing analysis processes.
Conduct thorough timing analysis, identify critical paths, and develop strategies to mitigate timing violations and improve overall design performance.
Stay abreast of industry trends and emerging technologies in STA and related fields, and incorporate best practices into the team’s workflow.
Prepare and present detailed timing reports and technical documentation to stakeholders
Foster a culture of innovation, collaboration, and continuous improvement within the STA team.

📌 Asic Physical Design Engineer Sta Bengaluru
🏢 Sandisk
📍 Bengaluru