08 Aug
|
Shervani Tech Hub
|
India
08 Aug
Shervani Tech Hub
India
Key Responsibilities
Design and implement DFT architecture for ASIC/SoC designs.
Develop and integrate Scan, MBIST, LBIST, Boundary Scan (JTAG), and Compression solutions.
Perform Scan insertion and DFT logic integration.
Generate and debug ATPG patterns to achieve target fault coverage.
Execute DFT verification using simulation and formal verification methodologies.
Analyze test coverage reports and optimize DFT implementation.
Debug DFT-related issues during pre-silicon verification and post-silicon validation.
Collaborate with RTL, Physical Design, Verification, Product Engineering, and Test teams.
Support silicon bring-up, characterization, and production test.
Ensure DFT implementation meets timing, area, and power requirements
📌 Dft Design Engineer Bengaluru (India)
🏢 Shervani Tech Hub
📍 India