08 Aug
|
Keen Heads
|
Chennai
08 Aug
Keen Heads
Chennai
Manage 2 -3 hierarchical blocks, DFT simulations, debug , pattern generation. Support scan chain insertion and post silicon debug
Desired Skills:
DFT logic integration and verification using testmax / tessent / modus
Experience on improving coverage.
Gate Level DFT verification with and without timing using vcs / ncsim.
Pattern generation, verification and delivery to ATE team.
Post silicon debug and support on failing patterns.
Valuable experience on EDA tools of reputed vendor like Mentor, Synopsis.
LBIST experience is a plus.
DFT mode STA and timing closure support is a plus
Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.
📌 Design Engineer Dft Chennai
🏢 Keen Heads
📍 Chennai