To play the role of Verification engineer at the Block level verification.
Develop verification test plans from design specifications.
Development of test settings using System Verilog and UVM verification methodologies.
Integration with RTL and basic simulation bring-up for the design.
Create multiple test cases as per test plan and launch regressions.
Generate Code/Functional coverage, analyze coverage results and correlate with the test plan.
Working the design team members to identify and quickly resolve problems with the design.
Bring a self-motivated and enthusiastic approach that will achieve any current requirements and overcome all challenge

Requirements/Qualifications:
Bachelor s/Master s degree in Electrical / Electronic Engineering or equivalent with atleast 10 year of work experience.
Domain Expertise : AHB, AXI, PCIe, USB and Ethernet.
Languages (must): Verilog, system Verilog
Methodologies (One of them is must): OVM/UVM
EDA Tools (One of them is must): Questasim,



VCS, NCSim, NCVerilog
Experience in developing Test Bench components in both block level and SOC level.
Experience in Creating test plan and Writing test sequence.
Functional Coverage, Code Coverage & Assertions (OVA, SVA, PSL) (Desirable)
Positive analytical and problem-solving skills
Excellent written and verbal communication in English.
Good teamwork and the desire to excel in a competitive environment.
Bachelors Level Degree (ECE, EE, CSE, IT / preferred specialization) with more than 10 years of work experience

Travel Time:

0% - 25%

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📌 Principal Engineer Verification Chennai (India)
🏢 Microchip Technology
📍 India