We are seeking highly experienced VLSI Signoff Engineers with strong hands-on expertise in Static Timing Analysis (STA), Physical Verification, and Power Supply Integrity (PSI) for advanced SoC designs. The ideal candidate will have deep signoff experience at advanced technology nodes and a solid understanding of foundry signoff methodologies.
Key Responsibilities:
- Perform STA signoff using PrimeTime, including setup/hold analysis and closure
- Handle OCV/AOCV/POCV analysis and drive ECO flows for timing closure
- Execute Physical Verification using Calibre (DRC, LVS, ERC)
- Perform Power Integrity / PSI signoff using Voltus: Static IR drop, Dynamic IR drop, Electromigration (EM) analysis
- Address advanced-node signoff challenges and ensure tape-out readiness
- Work closely with design, PD, and foundry teams to resolve signoff issues
- Apply and validate foundry rule decks and follow industry-standard signoff methodologies
Qualifications: 5+ years of exclusive, hands-on industry experience in VLSI signoff