Job DescriptionHi All,

NJob Location: Bangalore

NNotice Period: 15 days to 30 Days

NMinimum: 5+ Years

N1.Experience in Low powerRTL design, microarchitecture, synthesis, timing closure, Low power estimation. Should be proficient in Verilog.

N2. Should have experiencein optimization of microarchitecture and RTL for area and power reduction. Experience with Arithmetic units, Floating point datapath design is a plus.

N3. Should have experienceusing ASIC design tools such as VCS, Verdi, Design Compiler. Knowledge of power estimation tools(such as Spyglass, PTPX), scripting languages (Shell, Perl, Python), C language is a plus.

N4. Experience with hardware architecture exploration, performance modelling will be a big plus.

N5. Prior experience in Machine learning/Artificial Intelligence domain and/or DRAM Memory controllers is a plus.

N6.Must have experience inLint and CDC.

N7.Must have RTL Design worked on PCIe/CXL

NThanks,

nK Himabindu

📌 Senior Rtl Design Engineer (Bengaluru)
🏢 ACL Digital
📍 Bengaluru