About the Role:We are seeking a highly skilled Senior Physical Design Engineer with deep expertise in high-speed designs, particularly PCIe or other complex interfaces. The ideal candidate will have extensive experience in clocking, timing closure, and advanced physical design techniques. This role requires strong hands-on skills in Innovus (INVS) and Tcl scripting, along with the ability to drive solutions for challenging timing and clocking scenarios.

Key Responsibilities:

- Lead physical design activities focusing on complex clocking, CTS, and timing closure for high-speed interfaces.

- Perform interactive debug, clock clustering, delay balancing, and skew grouping to optimize design performance.

- Collaborate with RTL, verification, and validation teams to close interfaces with complex clocking structures.





- Develop and maintain Tcl scripts to automate physical design flows and debug processes.

- Provide technical guidance and mentorship to junior engineers in physical design best practices.

Qualifications:

- Strong hands-on experience with Cadence Innovus (INVS), particularly in CTS.

- Expertise in interactive debug, clock clustering, delay balancing, and skew grouping.

- Proven experience in closing complex interfaces with challenging clocking and timing requirements.

- PCIe or other high-speed interface experience is highly preferred; mandatory exposure to complex timing designs.

- Robust Tcl scripting skills to support automation and design optimization.

- Excellent problem-solving and analytical skills.

📌 Senior Physical Design Engineer – High-Speed Designs (PCIe) (Bengaluru)
🏢 Iospl Technology Services
📍 Bengaluru