ACL is hiring
Role: Memory Layout Engineer

Openings:
Experience: 5+ years
Notice Period: 15 days
Skill: Memory Layout Engineer
Current Location: Bangalore
Preferred Location: Bangalore

Job Description:
We are looking for a Memory Layout Engineer with hands-on experience in full-custom SRAM memory layout for advanced technology nodes. The ideal candidate should have strong expertise in custom layout implementation, physical verification, and tape-out of embedded memory macros.

Key Requirements:
Experience: 3–8 years of experience in SRAM Memory Layout.
Expertise: Robust expertise in the layout of SRAM architectures such as Single Port, Dual Port, Pseudo Dual Port, Register File, FIFO, and other embedded memory macros.
Technology Nodes: Hands-on experience with TSMC 2nm/3nm and/or Samsung 2nm/4nm technology nodes.
Lifecycle Ownership: Proven experience in the complete memory layout lifecycle, including floorplanning, device placement, routing, layout optimization, DRC/LVS/ERC closure,



parasitic extraction (PEX), and tape-out.
Technical Knowledge: Strong understanding of matching, symmetry, electromigration (EM), IR drop, density rules, antenna checks, ESD considerations, and advanced process design rules.
Tools: Experience with Cadence Virtuoso and physical verification tools such as Calibre (DRC/LVS/PEX).
Collaboration: Ability to work closely with memory design, circuit design, and verification teams to resolve layout-related issues and deliver high-performance, low-power, and manufacturable SRAM designs.
Optimization: Experience in layout optimization for area, performance, yield, and reliability.
Skills: Strong debugging and problem-solving skills with experience in physical verification issue resolution, ECO implementation, and successful tape-outs.

Interested can share your resume at: [email protected]

📌 Memory Layout engineer (Bengaluru)
🏢 ACL Digital
📍 Bengaluru