Memory layout Engineer (Hyderabad)

Memory layout Engineer (Hyderabad)

09 Aug
|
SysTechCorp
|
Hyderabad

09 Aug

SysTechCorp

Hyderabad

Title: Memory Layout Design Engineer.

Experience: 3+ years.

Location: Bangalore(F2F).

Roles and Responsibilities

Memory Leaf cell layout library design from scratch including top level integration.

Positive knowledge on different types of memory architectures.

Good knowledge in optimized layout design for better performance.

Sound knowledge & hands on experience in Finfet technology, layout design and DRC limitations.

Proficient in physical verification flow & debug, like DRC, LVS, ERC, Boundary conditions.

Proficient in Cadence Virtuoso layout editor and Calibre physical verification flow.

📌 Memory layout Engineer (Hyderabad)
🏢 SysTechCorp
📍 Hyderabad

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