09 Aug
|
Einfochips
|
Bengaluru
09 Aug
Einfochips
Bengaluru
ROLE & RESPONSIBILITIES:
Incumbent will be responsible for Scan insertion and validation, BIST, MBIST insertion and validation, ATPG, IP Tests and Pattern validation w/wo Timing, DFT mode timing Analysis and sign off.
Be responsible for a comprehensive DFT plan.
Incumbent to work with DFT and cross functional teams.
To architect and implement solutions for Scan and built-in self-test (Memory and Logic BIST) circuitry to test devices in the field.
ESSENTIAL SKILLS & EXPERIENCE:
Robust fundamentals on DFT and ASIC cycle.
Sound expertise in Tcl, Perl, Shell scripting. Technically sound & good team player.
Hands-on experience with DFT implementation using standard EDA and flow is a must.
📌 DFT Design Engineer (Bengaluru)
🏢 Einfochips
📍 Bengaluru