: Senior Design Verification (DV) Engineer

Role: Senior Design Verification (DV) Engineer

Location: Ahmedabad, Gujarat

Experience: 5–10 Years

Key Responsibilities

- Develop and maintain SystemVerilog (SV) and UVM-based verification environments.
- Perform ASIC, SoC, subsystem, and block-level verification.
- Develop testbenches from scratch and integrate with DUT.
- Execute coverage-driven verification methodology and achieve coverage closure.
- Verify and validate industry-standard protocols including PCIe/PCI-E, UCIe, CXL, USB, AMBA, MIPI, and Ethernet.
- Work with on-chip bus protocols such as AXI, AHB, and APB.
- Debug and resolve functional verification issues.
- Utilize EDA tools from Cadence, Synopsys, or Mentor Graphics.
- Develop and maintain automation scripts using Python, Shell,



Perl, or Makefile.

Required Skills

- Strong hands-on experience with SystemVerilog (SV) and UVM.
- Deep understanding of PCIe/PCI-E, UCIe, CXL, USB, AMBA, MIPI, and Ethernet protocols.
- Experience in ASIC, SoC, subsystem, and block-level verification.
- Solid knowledge of coverage-driven verification methodology.
- Experience in testbench development and DUT integration.
- Familiarity with AXI, AHB, and APB bus protocols.
- Experience with Cadence, Synopsys, or Mentor EDA tools.
- Proficiency in Python, Shell, Perl, or Makefile scripting.

📌 Design Verification Engineer (Gujarat)
🏢 Sourcebae
📍 Gujarat