10 Aug
|
AstraSilica Technologies
|
Bengaluru
10 Aug
AstraSilica Technologies
Bengaluru
Company Description AstraSilica Technologies is dedicated to advancing semiconductor technology to power next-generation applications in AI, IoT, 5G, and more. The company focuses on innovation, sustainability, and transforming industries such as healthcare and automotive through cutting-edge chip design and development. AstraSilica fosters a collaborative, inclusive culture where diverse perspectives drive better solutions and products. Team members are supported in their professional growth, whether they are early in their careers or experienced specialists. AstraSilica is actively expanding its engineering teams across domains including PD, RTL Design, STA, PV, Analog Layout, Memory Layout, Synthesis, DV, and DFT.
Role Description The Memory Layout and Analog Layout Engineer will be responsible for designing, implementing, and optimizing memory and analog circuit layouts for advanced semiconductor technologies. Day-to-day tasks include translating circuit schematics into robust physical layouts, performing layout verification, and collaborating with circuit design, DFT,
and physical design teams to meet performance, area, and reliability targets. The engineer will analyze and resolve layout-related issues, ensure adherence to design rules, and contribute to layout methodologies and best practices. This is a full time, on-site role based in Bengaluru, requiring close coordination with cross-functional engineering teams and participation in design reviews and project planning.
Qualifications
Strong foundation in analog design, including Analog Circuits and Analog Circuit Design.
Expertise in Power Management and related circuit design for low-power, high-efficiency systems.
Hands-on experience with Memory Layout and Analog Layout for advanced process nodes.
Proficiency with industry-standard EDA tools for layout and verification (e.g., Cadence Virtuoso, Mentor, Synopsys).
Solid understanding of semiconductor device physics, layout design rules, and parasitic effec
📌 Memory Layout and Analog Layout Engineer (Bengaluru)
🏢 AstraSilica Technologies
📍 Bengaluru