Hands on verification experience with C/C++/SystemVerilog testbench development.Hands on experience with coverage planning, coding and coverage closure.Experience with x86, ARM or any other industry standard microprocessor ISA.Experience with Cache, Coherency and Data-Consistency verification.Experience in clocking, reset, power-up sequences and power management verification.Knowledge of microprocessor design-for-debug (DFD) logic will be a plus.Understanding of low power design verification techniques is a plus.
Skills
Business Analysis, C++, Physical Design, RTL Design, SystemVerilog, Testing, VLSI
📌 Associate III (Hyderabad)
🏢 UST
📍 Hyderabad
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