Role Description
Who we are:
At UST, we help the world’s best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in 30+ countries, we build for boundless impact—touching billions of lives in the process. Visit us at UST.com.
Summary
UST is looking for…. Senior Physical Design Engineer
hands-on experience in the complete ASIC Physical Design flow, from netlist to GDSII, across advanced technology nodes.
The Prospect
We are seeking a highly skilled Senior Physical Design Engineer . The ideal candidate will have hands-on experience in the complete ASIC Physical Design flow, from netlist to GDSII, across advanced technology nodes. The role requires expertise in floorplanning, placement, clock tree synthesis (CTS), routing, timing closure, power optimization, and physical verification while working closely with RTL, DFT, and STA teams.
Key Responsibilities Perform end-to-end Physical Design implementation for complex SoC and ASIC designs. Develop floorplans considering power, timing, congestion, and area optimization. Execute placement, optimization, CTS, routing, and post-route optimization. Perform timing closure across multiple PVT corners and modes.
Resolve setup and hold timing violations. Conduct power optimization, IR drop analysis, and electromigration (EM) checks. Collaborate with RTL, DFT, STA, and Physical Verification teams to achieve design closure. Perform physical verification, including DRC, LVS, and antenna checks.
Analyze congestion and optimize design for performance, power, and area (PPA). Debug implementation issues and ensure high-quality GDSII delivery. Mentor junior engineers and support technical reviews. Participate in customer discussions, design reviews, and project planning.
Required Skills: Physical Design, LVS, DRC, Power Optimization
What We Believe
We’re proud to embrace the sa
📌 Project Lead II (Bengaluru)
🏢 UST
📍 Bengaluru