10 Aug
|
Weekday AI
|
Bengaluru
10 Aug
Weekday AI
Bengaluru
This role is for one of the Weekday's clients
Min Experience: 6+ years
Location: Bengaluru
JobType: full-time
We are looking for an experienced ASIC RTL Design Engineer with 6–10 years of hands-on experience in RTL design, SoC integration, and digital design methodologies. The ideal candidate will have strong expertise in SoC Integration, Reset Domain Crossing (RDC), and SoC Design, along with a solid understanding of RTL development, design verification, and industry-standard design practices.
You will work closely with architecture, verification, physical design, DFT, and system teams to develop robust, scalable, and high-performance SoC designs. This role requires solid analytical and problem-solving skills, attention to design quality, and the ability to contribute across different stages of the ASIC development lifecycle.
Key Responsibilities
Design, develop, and maintain high-quality RTL designs for complex ASIC and SoC products using Verilog/SystemVerilog.
Own and contribute to SoC integration, including integration of IPs, subsystems, interfaces, clocks, resets,
and other system-level components.
Analyze and resolve Reset Domain Crossing (RDC) issues and ensure robust reset architecture across the SoC.
Participate in SoC design and micro-architecture activities, translating architectural specifications into efficient and synthesizable RTL.
Develop RTL modules with a strong focus on functionality, performance, power, area, and design quality.
Integrate and configure third-party and internally developed IPs into complex SoC environments.
Review design specifications, interface definitions, block-level architectures, and integration requirements.
Collaborate with verification teams to define design requirements, identify corner cases, and support functional verification.
Debug RTL and integration issues using simulation, waveform analysis, lint reports, and other design-quality tools.
Participate in design reviews, code reviews, and technical discussions to en
📌 ASIC RTL Design Engineer (Bengaluru)
🏢 Weekday AI
📍 Bengaluru