Lead Engineer (Hyderabad)

Lead Engineer (Hyderabad)

10 Aug
|
Silicon Labs
|
Hyderabad

10 Aug

Silicon Labs

Hyderabad

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com.
The Role :
In this role, you will work on low-power design verification for complex SoCs, ensuring robust and power-effective silicon. You will focus on validating power intent and low-power features using UPF/CPF methodologies across the design lifecycle.
Meet the Team :
The Design Verification team collaborates closely with RTL, architecture, and physical design teams to deliver high-quality silicon. We focus on coverage-driven verification and advanced low-power methodologies.
Responsibilities :




Understand and verify power domains and power intent (UPF/CPF)
Develop and execute test plans for low-power modes and states
Own end-to-end DV: testbench development, testcases, assertions, debugging (RTL/UPF)
Drive functional and assertion coverage closure
Build and enhance SystemVerilog/UVM verification environments
Perform power-aware verification and debug complex issues
Collaborate with cross-functional teams and explore advanced DV methodologies
Requirement :
Minimum Qualifications:
BS/MS in Electrical or Computer Engineering (or related field)
6–8 years of experience in design verification
Strong SystemVerilog/UVM skills
Experience with assertion-based and coverage-driven verification
Solid understanding of low-power design techniques
Experience with UPF/CPF-based verification
Knowledge of low-power SoC constructs (clock gating, isolation, level shifters, retention)
Strong debuggin

📌 Lead Engineer (Hyderabad)
🏢 Silicon Labs
📍 Hyderabad

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