A Senior DFT (Design-for-Test) Engineer is responsible for architecting, implementing, and validating test methodologies in complex SoC/ASIC designs, ensuring manufacturability, reliability, and efficient silicon bring-up. The role blends deep technical expertise in scan insertion, ATPG, MBIST, and test pattern validation with cross-functional collaboration across RTL, verification, and physical design teams.

DFT Architecture & Implementation

Define and implement DFT methodologies for SoCs, MCUs, or test chips
Insert scan chains, boundary scan, MBIST, and repair logic at RTL/gate level
Architect cutting-edge DFT techniques for advanced process nodes.

Test Pattern Development & Validation

Generate ATPG patterns for stuck-at, transition, and path delay faults
Debug test pattern issues during silicon bring-up




Ensure highest stability and coverage of test patterns on ATE (Automatic Test Equipment).

Cross-Functional Collaboration

Work closely with RTL design, verification, physical implementation, and test engineering teams
Support silicon characterization and yield improvement activities
Contribute to overall microcontroller or SoC DFT methodology
Bachelor's/master's in electrical engineering, Microelectronics, or related field

Requirements

Typically, 5-8 years in DFT for complex SoCs/ASICs
Experienced in Scan insertion, ATPG, MBIST, boundary scan, JTAG
Debugging silicon test issues and yield analysis
Experience in Scripting/ programming using Python, Perl, TCL

📌 DFT Engineer (Chennai)
🏢 Erbity
📍 Chennai