Hands-on experience in SoC-AMS testbench development
Strong expertise in SV/UVM-based mixed-signal testbench development from scratch
Behavioral modeling using SV-RNM, Verilog-AMS, wreal, and electrical
Experience with Cadence tools: Virtuoso, ADE Assembler, Xcelium, VIVA, SimVision
Robust fundamentals in analog blocks, digital design flow, and top-level integration
Good debug skills across waveforms, schematic simulations, and model behavior
Prior AMS DV Lead experience will be a strong advantage