Solid proficiency in SystemVerilog and HDL languages.Hands-on experience with UVM or other industry-standard verification methodologies.
Strong object-oriented programming skills using SystemVerilog and C++.
Ability to write and interpret architectural/design specifications and verification requirements.
Experience in writing verification test plans.
Proficiency in developing complex simulation test benches.
Ability to implement directed and constrained-random test cases.
Experience with functional and code coverage collection, analysis, and closure.
Strong debugging skills for simulation issues, test cases, tools, and DUT (Device Under Test).
Extensive experience in at least one of the high speed protocol related verification (PCIe/Ethernet/DDR/UCIe/CXL/USB).
Proficiency in scripting languages such as Perl, Shell, and Python.
📌 Sr. Verification Engineer (Hyderabad)
🏢 Source right
📍 Hyderabad
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