Description

Job Summary

We are seeking a skilled and motivated Senior Digital IC Design Engineer with over 5 years of experience in digital design and proven expertise in memory IP integration (SRAM, ROM, EEPROM, OTP/NVM). The candidate will play a key role in the development, integration, and verification of memory subsystems in advanced SoC platforms.

Key Responsibilities

- Own and drive the integration of memory IPs into larger digital subsystems and SoC platforms.

- Collaborate with memory IP teams to understand interface requirements, timing constraints, and test features.

- Perform RTL design, lint, CDC, and synthesis for digital logic blocks interacting with embedded memories.

- Define and execute design verification plans in coordination with the verification team.

- Interface with physical design and validation teams to ensure successful implementation and bring-up.





- Support post-silicon debug for memory interface-related issues.

- Contribute to technical reviews, architecture discussions, and documentation of design flows

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Responsibilities

Soft Skills

- Robust communication and documentation skills.
- Collaborative and proactive problem solver.
- Capable of mentoring junior engineers and participating in design reviews.

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Qualifications

Required Qualifications

- Bachelor’s or Master’s degree in Electrical Engineering or related field.
- 5+ years of experience in digital ASIC design, preferably with a focus on memory IP integration.
- Strong RTL design skills in Verilog/SystemVerilog.
- Proficient in EDA tools for synthesis, lint, and static timing analysis.

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📌 Sr Principal ASIC / RTL Design Engineer (Bengaluru)
🏢 Important Company of the Sector
📍 Bengaluru