? We Are Hiring | Senior PCIe Design Verification Engineers | Bangalore
Are you passionate about validating next-generation high-speed interconnect technologies and enabling world-class silicon products? Join Silicon Patterns and become part of a team driving cutting-edge semiconductor innovation.
We are looking for highly skilled PCIe Design Verification Engineers with robust expertise in PCIe protocol verification across Gen4, Gen5, and Gen6 standards. This is an exciting opportunity to work on advanced SoC and IP verification projects for leading semiconductor customers.
? Location: Bangalore
? Experience: 5+ Years
⏳ Notice Period: Immediate to 60 Days Preferred
? Domain: Semiconductor | Design Verification
Role Overview
As a PCIe Verification Engineer, you will be responsible for architecting and executing comprehensive verification strategies for PCIe-based IPs and subsystems. You will collaborate closely with design, architecture, and validation teams to ensure first-pass silicon success through robust verification methodologies and protocol compliance validation.
Key Responsibilities
Develop and maintain advanced verification environments using SystemVerilog and UVM.
Verify PCIe Gen4/Gen5/Gen6 Controller, PHY, Endpoint, Root Complex, and Subsystem-level designs.
Create reusable verification components, scoreboards, monitors, checkers, and protocol-specific VIP integrations.
Design and execute constrained-random and directed test scenarios to achieve functional and code coverage goals.
Perform protocol compliance verification, error injection, LTSSM validation, link training, power management, and interrupt verification.
Debug complex RTL and verification issues using waveform analysis and simulation tools.
Review architecture specifications and develop detailed verification plans and test strategies.
Collaborate with design, firmware, and post-silicon teams to identify and resolve functional issues.
Drive coverage closure, regression management, and verif