WeAreIn to make sure that our circuits are designed to perfection. Are you in?
We are seeking a highly motivated, talented individual to join our Silicon Engineering team as a Trainee Engineer - Digital Design Verification. In this role, you will work on Graphics /Security IP, helping to ensure the functional correctness of complex, next-generation architecture. You will learn from industry experts and gain hands-on experience building advanced simulation and emulation testbenches using industry-standard methodologies.
Your role
Key responsibilities in your recent role
Testbench Development: Assist in developing, maintaining, and enhancing block-level and chip-level simulation testbenches (TB)
UVM Architecture: Write scalable verification components, including drivers, monitors, predictors, and scoreboards using SystemVerilog (SV) and UVM.
Emulation Platforms: Collaborate with senior engineers to bring up emulation testbenches for hardware-accelerated verification and pre-silicon validation.
Graphics IP Verification: Learn the intricate architecture of Graphics IPs (pipelines, shaders,
or memory controllers) and map out comprehensive verification plans.
Debug & Coverage: Run regressions, debug hardware failures using waveform viewers, and write functional coverage covergroups to achieve 100% verification closure.
Your profile
Qualifications and skills to help you succeed
Education: Bachelor’s or master’s degree in Electronics Engineering, Computer Engineering, Computer Science, or a related field (Graduation date within the last 12 months).
Languages: Robust foundational knowledge of SystemVerilog (SV).
Methodology: Exposure to UVM (Universal Verification Methodology) through university coursework, lab projects, or internships.
Core Concepts: Solid understanding of digital logic design, computer architecture, and FIFO/arbitration mechanisms.
Scripting: Basic proficiency in scripting languages like Python, Perl, or Bash for automation.