About the Role
We are expanding our semiconductor engineering team and looking for experienced Senior Design Verification Engineers to join us in Pune.
If you have strong expertise in ASIC/SoC Design Verification, SystemVerilog, UVM, and high-speed protocols such as PCIe, UCIe, CXL, or RISC-V, this is an excellent opportunity to work on next-generation semiconductor products alongside industry experts.
Key Responsibilities
Develop and maintain robust UVM-based verification environments for complex IP and SoC designs.
Create and execute comprehensive verification plans and test strategies.
Perform functional verification using SystemVerilog and industry-standard methodologies.
Develop constrained-random testbenches and drive functional coverage closure.
Debug RTL, testbench, and simulation issues to ensure high-quality silicon.
Verify high-speed interface protocols and processor-based subsystems.
Collaborate with RTL designers, architects, and cross-functional engineering teams throughout the product development lifecycle.
Contribute to regression management, automation,
and verification methodology improvements.
Required Qualifications
Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Science, or a related field.
5–10 years of hands-on experience in ASIC/SoC Design Verification.
Robust expertise in:
SystemVerilog
UVM Methodology
C/C++
Experience with one or more of the following protocols:
PCIe (PCI Express)
UCIe
CXL
RISC-V
Good understanding of digital design fundamentals and ASIC verification flows.
Experience with IP and SoC verification methodologies.
Hands-on experience with on-chip bus protocols such as:
AXI
AHB/APB
Strong debugging, problem-solving, and analytical skills.
Preferred Skills
Experience with any of the following will be an added advantage:
USB or other industry-standard interface protocols
Functional Coverage and Constrained Random Verification
Assertion-Based Verification (SVA)
Python or Perl scripting for automation