Design Eng (Pune)

Design Eng (Pune)

10 Aug
|
Lattice Semiconductor
|
Pune

10 Aug

Lattice Semiconductor

Pune

Lattice Overview
There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D;, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.
Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.
Job Description:
Role specifics:
This is a full time individual contributor position located in Pune, India.




This is a senior technical lead role with end-to-end ownership from microarchitecture through tapeout, working alongside a small, high-impact design team.
The qualified candidate will be an expert in RTL design, best-in-class coding styles, algorithms, and both Verilog and System Verilog.
The qualified candidate will be expert in SoC integration and associated quality checks including lint, CDC, RDC, SDC etc.
The role requires to work with architecture team to define micro architect and design spec.
The successful candidate will be open and willing to both (a) teach best-known-methods to an existing design team and (b) learn from the team about the complications of highly programmable FPGA fabrics. This role carries the need to be both a strong educator and an open-minded student.
Responsibilities
Own RTL design and microarchitecture of the processor subsystem, including embedded MCU cores, bus fabric, and DMA infrastructure
Work with Architecture tea

📌 Design Eng (Pune)
🏢 Lattice Semiconductor
📍 Pune

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