Job Requirements
At Quest Global, it’s not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.
Job Summary
We are looking for an experienced Lead Engineer - Physical Verification to drive signoff-quality physical verification for advanced-node ASIC/SoC designs. The candidate will be responsible for DRC, LVS, ERC, Antenna, Density, and Physical Verification closure while collaborating with Physical Design, Layout, Foundry, and CAD teams. The ideal candidate should possess solid expertise in foundry rule decks, advanced process technologies, and PV signoff methodologies.
Key Responsibilities




Lead block-level and full-chip Physical Verification activities.
Perform and debug:
Design Rule Check (DRC)
Layout vs Schematic (LVS)
Electrical Rule Check (ERC)
Antenna Verification
Density Verification
Metal Fill Verification
Analyze and resolve physical verification violations to achieve signoff.
Collaborate with Physical Design and Layout teams to ensure clean tapeout readiness.
Develop and maintain PV automation scripts and methodologies.
Work closely with foundries to understand and resolve process-specific rule issues.
Drive turnaround time improvements for large SoC verification runs.
Review and optimize rule deck execution and runtime efficiency.
Support post-layout verification and tapeout activities.
Mentor junior engineers and provide technical leadership.
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📌 Lead Engineer (Hyderabad)
🏢 Quest Global
📍 Hyderabad