Key Responsibilities
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Create and optimize floorplans for analog and mixed-signal blocks in advanced 7nm FinFET technology.
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Translate sub-block schematics into physical layouts while maintaining hierarchy and design intent.
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Perform detailed transistor-level and block-level layout implementation for high-speed circuits.
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Ensure layout matches parameterized devices (PCells) and simulation hierarchy on a one-to-one basis.
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Follow design documentation, review comments, customer feedback, and back-annotation requirements during layout execution.
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Perform and resolve Design Rule Check (DRC) violations until the layout is fully clean.
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Perform and resolve Layout Versus Schematic (LVS) discrepancies until successful signoff.
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Ensure layouts comply with all foundry-specific design rules and reliability requirements.
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Generate extracted netlists for post-layout simulations and back-annotation activities.
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Work closely with Design Engineers (DEs) to support post-layout verification and performance closure.
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Document layout methodologies, notes,



and implementation details in block review documents.
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Participate in design reviews and implement corrective actions resulting from layout reviews.
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Optimize layout for area, matching, parasitics, signal integrity, electromigration (EM), and manufacturability.
Required Qualifications
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Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Microelectronics, or related field.
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Robust experience in 7nm FinFET technology node layout development.
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Proven expertise in high-speed analog and mixed-signal layout design.
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Hands-on experience with advanced node layout challenges including:
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Multi-patterning awareness
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Device matching
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Parasitic optimization
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Reliability rules
cyient.com
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Strong understanding of:
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DRC
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LVS
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Parasitic extraction (PEX)
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ERC checks
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Experience generating extracted netlists and supporting post-layout simulations.
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Excellent understanding of analog layout techni

📌 Senior Analog Layout Engineer (Bengaluru)
🏢 Cyient
📍 Bengaluru