The Role and Impact As a Mixed Signal Logic Design Engineer, you will play a
pivotal role in shaping the future of industry-leading technologies by
contributing to the development of high-speed, low-power IPs for next-generation
products. You will work in a dynamic, innovative environment, collaborating with
cross-functional teams to deliver robust and efficient mixed signal designs. By
owning and delivering the logic design of Mixed Signal IPs, you will directly
influence Intel's mission to create world-changing technology that enables
global progress and enriches lives. Key Responsibilities - Define and implement
microarchitecture and RTL designs for mixed signal and high-speed IP blocks
using System Verilog. - Collaborate closely with architecture and system teams
to optimize power, performance, and area for IP designs. - Develop and utilize
automation flows for IP logic design, ensuring high-quality RTL through tools
such as Lint, CDC, and synthesis QA checks. - Conduct power and performance
analysis,
driving improvements in area and power efficiency across designs. -
Review verification plans and resolve RTL issues to ensure feature correctness
and design integrity. - Support SoC teams, ensuring seamless integration and
high-quality delivery of IP modules. - Innovate and implement automated
solutions to streamline coverage closure and timing convergence.
QUALIFICATIONS:
Minimum Qualifications - Bachelor's or Master's degree in Electrical or Computer
Engineering, or a closely related field. - 4-12 years of experience with a
Bachelor's degree or 3-10 years of experience with a Master's degree. - Robust
expertise in RTL development using System Verilog. - Proficiency in low-power
design techniques, including UPF, clock gating, and multiple clock domain
design. - Hands-on experience with front-end design tools such as Spyglass, VC
Lint, CDC, and synthesis tools. - Solid understanding of state machine design,
simulation, and debuggi