Overview
Rambus, a premier chip and silicon IP provider, is seeking to hire a motivated full time Principal Design engineer to join our PCIe IP design team. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.
This full-time position will allow the candidate to contribute to the architecture, design of next generation IPs, targeting the latest developments in PCIe standards. This position will also be involved in prototyping these IPs on cutting edge FPGAs. The candidate will work closely with local teams as well as with multi-cultural, multi-national colleagues.
Responsibilities
Contribute to the architecture and micro-architecture of next generation PCIe IP
Implement these designs in System Verilog
Collaborate with the verification team to verify the IPs
Participate in prototyping of the IPs in cutting edge FPGAs
Contribute to support of existing generations of the IPs
Qualifications
RTL coding: Verilog / System Verilog
Master's degree or PHD in Electrical Engineering,



Computer Engineering or equivalent.
8+ years of experience with RTL Design
Good English skills, communication skills, and willingness to work with an international team.
Additional Desirable skills:
Knowledge of PCIe / CXL
Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrow’s systems.
Rambus offers a competitive compensation package, including base salary, bonus, equity and employee benefits.
Rambus is committe

📌 PE Logic Design (India)
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📍 India