Senior Physical Design Engineer

Location: Bengaluru, India

Experience: 4–8 Years

Role

Join our Physical Design team to drive implementation and signoff of complex SoCs across advanced technology nodes. You will own physical design closure with a strong focus on STA, EM/IR, timing closure, and physical signoff .

What You'll Do

- Drive RTL-to-GDSII Physical Design for complex SoC/IP blocks.
- Perform Floorplanning, Placement, CTS, Routing, Physical Verification, and ECO closure .
- Own Static Timing Analysis (STA) and timing closure across MMMC scenarios.
- Analyze and resolve EM/IR , Signal Integrity, Crosstalk, and Power Integrity violations.
- Drive physical signoff including DRC, LVS, Antenna, ERC , and QoR optimization.
- Collaborate with RTL, Synthesis, DFT, and Full-Chip teams to achieve PPA and tapeout targets.
- Develop automation using Tcl/Python/Perl to improve design productivity.

What You Bring





- 4–8 years of hands-on experience in ASIC/SoC Physical Design .
- Strong expertise in Floorplanning, Placement, CTS, Routing, Timing Closure, and ECO .
- Excellent understanding of STA, MMMC, SDC, EM/IR, Signal Integrity, Crosstalk, and Physical Signoff .
- Hands-on experience with Cadence Innovus or Synopsys ICC2/Fusion Compiler .
- Solid knowledge of PrimeTime/Tempus , RedHawk/Voltus , and Calibre signoff flows.
- Experience with advanced technology nodes (7nm/5nm/3nm) is preferred.
- Good scripting skills in Tcl, Python, or Perl .

Preferred Qualifications

- Exposure to Low Power (UPF/CPF) , CDC/RDC, and multi-voltage designs.
- Experience with CPU, GPU, AI/ML, Networking, or Automotive SoCs.
- Strong debugging, problem-solving, and cross-functional collaboration skills.

📌 Senior Physical Design Engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru