Sr Staff - Physical Implementation Flow (experience - 8+ Years)
We Are:
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
You Are:
You are a highly skilled and experienced ASIC Digital Design Engineer passionate about working on the latest processes for physical implementation flows and cutting-edge technology nodes. You thrive in dynamic environments and excel in collaborating with functional teams to optimize and develop Next Gen PCI/CXL/IDE Controller IPs. You have a strong focus on Timing Closure and are adept at defining signoff criteria. Your background includes extensive experience with ASIC design flow, hierarchical physical design strategies, and a deep understanding of sub-micron technology issues.
You possess a strong knowledge of timing analysis, constraints management, and various verification strategies, including Primepower-based power analysis. Your scripting skills are excellent, and you are creative, self-motivated, and able to work both independently and as part of a team. Your communication skills, both verbal and written, are outstanding, and you have a desire to understand RTL/Timing signoff criteria.
What You’ll Be Doing:
Working on new processes for physical implementation flows and cutting-edge technology nodes.
Collaborating with functional teams to optimize and develop Next Gen PCI/CXL/IDE Controller IPs.
Defining signoff criteria with a strong focus on Timing Closure.
Maturing the physical implementation guide used for customers and internal hardening teams.
Participating in next-generation physical design methodology and flow development.
Performing physical design implementation, inc