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The project involves validating all the features and interfaces supported on the FPGA by creating and using validation designs that are partitioned into RTL and Embedded Processor Application.

Test and debug the silicon on board with the help of lab equipment and protocol testers. Typical day for Validation Engineer would include following activities:

- Validation design creation using our FPGA design flow
- RTL and Embedded C based test design development
- Validation of all features of FPGA
- Debug and root cause analysis, validating workaround and fixes
- Study of specification and validation plans
- Create and maintain required hardware setup, bring up the silicon and validate use cases capture results
- Documentation of test results, reviewing with stakeholder and getting sign-off
- Develop automation and regression design and flow
- File Bugzilla/jira tickets during the design creation and validation phase, perform the experiments required to isolate and debug.

Requirements/Qualifications:

- Strong hands-on FPGA Silicon validation experience
- Experience in using Synthesis, Placement constraints.



STA constraint definition and Timing closure for high-speed designs
- Solid technical background in silicon validation, functional validation, failure analysis and debug
- Excellent Board level debug capabilities in lab environment: hands-on troubleshooting skills for digital logic and analog circuit on PCBs using oscilloscopes, digital analyzers, protocol exercisers and analyzers, integrated logic analyzers (e.g. Identify, Chipscope, SignalTap, Reveal)
- Working knowledge on embedded software C/C++ is also a plus
- Basic knowledge of embedded processors such as and familiarity with AMBA protocols APB, AHB, AXI and peripherals such as SPI, I3C and UART
- Hands-on systems level design and debug experience with any few of the following high-speed serial communications protocols:
- PMA features, Eye capture, equalization and debug
- DDR 4/5
- 100G/50G/40G/25G/10G Ethernet
- USB3.2, DisplayPort, HDMI
- JESD204B, JESD204C
- Working knowledge of SERDES architecture, Equalization settings and debug
- PCIe Gen4/5

📌 Senior FPGA Engineer - RTL/Embedded C (India)
🏢 SQUARE ROOT CONSULTING
📍 India